1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to repeater circuits.
2. Description of the Related Art
As integrated circuit (IC) technology advances, the speed at which IC's operate increases while operating voltages generally decrease. As such, the distance at which signals must propagate on a die become an increasingly important factor to consider in IC design. At longer distances, on-die interconnects between a transmitter and a receiver can develop enough resistance and enough capacitance that the signal transition at the receiver can be adversely affected. Excessive propagation delay across a long signal interconnect can affect the transition at the receiver in terms of both timing and voltage levels. For example, a signal that propagates too slowly across an interconnect may in some cases not allow sufficient set-up and hold time for the receiver to properly transition from one logic level to another. Furthermore, a slow transition can cause crowbar currents in some receivers, which can lead to increased power consumption and may further lead to circuit damage in more severe cases.
In order to combat the negative effects of long signal interconnects, repeater circuits may be implemented. More particularly, repeater circuits may be placed along a signal path between a transmitter and receiver, effectively breaking a single interconnect into two or more interconnects. In such a configuration, repeater circuits may overcome some of the problems of resistance and capacitance that would be present in a single signal interconnect, and may further cause faster transition times at the receiver.
Repeater circuits may be simple or complex. The simplest interconnect circuits may be implemented using an inverter, with a double inverter (i.e. a buffer) being an alternative if no logical inversion is desired. FIG. 1 is a schematic diagram of a more complex repeater circuit. In the embodiment shown, repeater circuit 200 may change the state of a signal on its output node (‘Out’) responsive to a change on its input node (‘In’). The input signal may propagate through weak keeper 205 to the output node. The output signal may also be driven on the output node by output circuit 225. For example, if the input signal transitions from a low to a high, transistor N201 is activated, and a pull-down path is provided between node dp and ground through N201 and N202. As a result, P203 is activated and drives the output node high. After a delay time determined equal to the propagation delay through delay circuit 210, transistor N202 may be deactivated while transistor P202 is activated, pulling node dp high. A high-to-low transition of the input signal may occur in a similar manner, with N206 driving the output node low until turned off via the feedback path through delay circuit 210.
The use of repeater circuit 200 may provide certain advantages over simpler repeater circuits, such as the aforementioned buffers and inverters. For example, repeater circuit 200 may be less susceptible to crowbar currents than a buffer or an inverter. Furthermore, power consumption may be reduced, since the two output devices (which are typically much larger than other devices in the circuit) are not active at the same time, thereby preventing crowbar power consumption. Instead, the output devices may provide sufficient drive to overcome the resistance and capacitance inherent in the signal interconnect long enough to enable a timely transition at the receiver, and then turned off once the output is present on the output of weak keeper 205.
In some cases, the length of a signal path between two points on an IC die may have a propagation time that is longer than a clock cycle at which the IC operates. Accordingly, it may be necessary to store the state of the transmitted signal across a clock boundary. One solution for such a situation is to use a flip-flop, rather than using a repeater circuit.